An entropy measure for the complexity of multi-output Boolean functions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Randomized algorithms
Delay estimation VLSI circuits from a high-level view
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Space and time compaction schemes for embedded cores
Proceedings of the IEEE International Test Conference 2001
Self-dual parity checking-A new method for on-line testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Spatial Entropy - A Unified Attribute to Model Dynamic Communication in VLSI Circuits
Spatial Entropy - A Unified Attribute to Model Dynamic Communication in VLSI Circuits
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
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We discuss the problem of parity tree selection for losslesscompaction of the output responses of a circuit. Earliermethods assume off-chip storage of the correct compactedresponses and therefore minimize the number of necessaryparity trees. In contrast, our method targets on-chip generationof the correct compacted responses and therefore minimizesthe actual implementation cost of the correspondingparity prediction functions. We present a systematic searchapproach that exploits the correlation between the hardwarecost of a function and its entropy, in order to select paritytrees that minimize the incurred cost, while achieving losslesscompaction. Experimental results demonstrate that ourmethod achieves significant hardware reduction over methodsthat minimize the number of parity trees.