On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
On the design of self-checking functional units based on Shannon circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
Cost-Driven Selection of Parity Trees
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits.