Shorts in self-checking circuits
Journal of Electronic Testing: Theory and Applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Self-checking combinational circuit design for single and unidirectional multibit error
Journal of Electronic Testing: Theory and Applications
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
IEEE Transactions on Computers
Concurrent Checking of Clock Signal Correctness
IEEE Design & Test
Synthesis of Multi-level Self-Checking Logic
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Designing Networks with Error Detection Properties through the Fault-Error Relation
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Testing scheme for IC's clocks
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Self-dual parity checking-A new method for on-line testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy-reliability trade-off for NoCs
Networks on chip
A statistical model for estimating the effect of process variations on crosstalk noise
Proceedings of the 2004 international workshop on System level interconnect prediction
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
VEBoC: variation and error-aware design for billions of devices on a chip
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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