Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
Proceedings of the 31st annual international symposium on Computer architecture
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis of system bus transaction vulnerability in systemC TLM design platform
CEA'09 Proceedings of the 3rd WSEAS international conference on Computer engineering and applications
Simulation-based verification of the MOST NetInterface specification revision 3.0
Proceedings of the Conference on Design, Automation and Test in Europe
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System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls for focus on reliability issues in such bus based systems. In this paper, we provide a detailed analysis of different kinds of errors and the susceptibility of such systems to such errors on various components that the bus comprises of. With elaborate experiments we determine the effect of a single bit error on the bus system during the course of different transactions. The work demonstrates the fact that only a few signals in a bus system are really critical and need to be guarded. Such transaction based analysis helps us to develop an effective prediction methodology to predict the effect of a single bit error on any application running on a bus based architecture. We demonstrate that our transaction based prediction scheme works with an average accuracy of 92% over all the benchmarks when compared with the actual simulation results.