Analyzing Partition Testing Strategies
IEEE Transactions on Software Engineering
Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Using TLM for Exploring Bus-based SoC Communication Architectures
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Coverage Driven Verification applied to Embedded Software
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Fault Injection Techniques and their Accelerated Simulation in SystemC
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Verification of temporal properties in automotive embedded software
Proceedings of the conference on Design, automation and test in Europe
A NoC Simulation and Verification Platform Based on SystemC
CSSE '08 Proceedings of the 2008 International Conference on Computer Science and Software Engineering - Volume 03
FGCN '08 Proceedings of the 2008 Second International Conference on Future Generation Communication and Networking - Volume 02
Hardware Design Verification: Simulation and Formal Method-Based Approaches
Hardware Design Verification: Simulation and Formal Method-Based Approaches
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Evaluation of Random Testing
IEEE Transactions on Software Engineering
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Design and specification errors are hard to find in the traditional automotive system design flow. Consequently, these errors may be detected very late e.g. in a hardware prototype or even worse in the final product. In order to allow the verification of distributed embedded systems in early design phases, this work proposes a flexible and efficient virtual prototyping approach in order to check the consistency of system specifications. Our virtual prototyping approach has been applied to the Media Oriented Systems Transport (MOST) specification revision 3.0 and verifies the influence of two newly specified algorithms, namely Ring Break Diagnosis and Sudden Signal Off detection, with respect to numerous network configurations. In total we have verified the specification using more than 105 automatically generated network configurations. The overall costs for network modelling and verification compared to cost-expensive error detection and correction at later design phases have been significantly reduced.