Testing scheme for IC's clocks

Authors:
M. Favalli;C. Metra
Affiliations:
DEIS - University of Bologna, Viale Risorgimento, 2, 40136 Bologna, Italy;DEIS - University of Bologna, Viale Risorgimento, 2, 40136 Bologna, Italy
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

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Abstract

This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.