A Totally Self-Checking Error Indicator
IEEE Transactions on Computers
On error indication for totally self-checking systems
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
A methodology for testability enhancement at layout level
Journal of Electronic Testing: Theory and Applications
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
Digital Technical Journal - Special 10th anniversary issue
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testing scheme for IC's clocks
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
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This paper proposes an on-line testing scheme for permanentand temporary faults which affect signals of theclock distribution network of synchronous systems, andwhich make them be stuck-at, or change with incorrect frequencyor duty-cycle. By means of straightforward modifications,the proposed scheme can be also used to detecton-line undesired skews between couples of clock signals.