On the Design of Combinational Totally Self-Checking 1-out-of-3 Code Checkers
IEEE Transactions on Computers
A Hyper Optimal Encoding Scheme for Self-Checking Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Highly testable and compact 1-out-of-n code checker with single output
Proceedings of the conference on Design, automation and test in Europe
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
Concurrent Checking of Clock Signal Correctness
IEEE Design & Test
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Self-exercising self testing k-order comparators
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Integrating on-chip temperature sensors into DfT schemes and BIST architectures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Modular TSC Checkers for Bose-Lin and Bose Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On-Line Testing Scheme for Clock's Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A self-checking PLA automatic generator tool based on unordered codes encoding
EURO-DAC '91 Proceedings of the conference on European design automation
Fault-tolerant platforms for automotive safety-critical applications
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing: Theory and Applications
Proceedings of the 1st workshop on Architectural and system support for improving software dependability
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them
Journal of Electronic Testing: Theory and Applications
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Strongly code-disjoint (SCD) checkers are defined and shown to include totally self-checking (TSC) code-disjoint checkers. This type of checker is the natural companion of strongly fault-secure (SFS) networks. SCD checkers are the largest class of checkers with which a combinational system may achieve the TSC goal. Some examples are given to illustrate the design of SCD checkers.