Novel Berger code checker

Authors:
C. Metra;M. Favalli;B. Ricco
Affiliations:
-;-;-
Venue:
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Year:
1995

Citing 7
Cited 2

Design of Fast Self-Testing Checkers for a Class of Berger Codes

IEEE Transactions on Computers
Strongly Code Disjoint Checkers

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Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

Journal of Electronic Testing: Theory and Applications
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning

IEEE Transactions on Computers
"Resistive Shorts" Within CMOS Gates

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Inductive Fault Analysis of MOS Integrated Circuits

IEEE Design & Test
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes

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Intermediacy Prediction for High Speed Berger Code Checkers

Journal of Electronic Testing: Theory and Applications
16.1 Novel Single and Double Output TSC Berger Code Checkers

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

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Abstract

This paper presents a novel checking circuit for Berger codes, with any value of k (also k=2/sup r-1/), which is TSC with respect to a wide set of realistic faults including all possible stuck-ats, transistors stuck-on/stuck-open, as well as several likely to occur resistive bridgings. With respect to the other alternative implementations the proposed checker features the advantage of being inherently more testable, and of requiring lower area overhead.