Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Error-Control Coding in Computers
Computer
A methodology for testability enhancement at layout level
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Fast and area-time efficient Berger code checkers
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Data Integrty in Digital Optical Disks
IEEE Transactions on Computers
Intermediacy Prediction for High Speed Berger Code Checkers
Journal of Electronic Testing: Theory and Applications
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes"
Journal of Electronic Testing: Theory and Applications
Berger code-based concurrent error detection in asynchronous burst-mode machines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor stuck-on, resistive bridging faults and breaks. A benefit of the proposed type-I single and double output checkers is that all faults are testable by a very small set of code words the number of which does not increase with the information length, that is, the checkers are C-testable. The proposed double output checkers are two-times faster than the corresponding single output checkers, but require for their implementation twice as many transistors as the single output checkers. The proposed single output checkers are the first known TSC Berger code checkers in the open literature, while the type-I single output checkers are near optimal with respect to the number of the transistors required for their implementation. The checkers of this paper, with either, single or double output are significantly more efficient, with respect to the implementation area and speed, than the already known from the open literature Berger code checkers.