Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Theory and Design of t-Error Correcting and d(dt)-Unidirectional Error Detecting (t-EC d-UED) Codes
IEEE Transactions on Computers - Fault-Tolerant Computing
Error-control coding for computer systems
Error-control coding for computer systems
On t-Error Correcting/All Unidirectional Error Detecting Codes
IEEE Transactions on Computers
Theory and Design of t-Error Correcting/d-Error Detecting (d
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient fault tolerant cache memory design
Microprocessing and Microprogramming
Probability to Achieve TSC Goal
IEEE Transactions on Computers
Optimal Unidirectional Error Detecting/Correcting Codes
IEEE Transactions on Computers
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Modular TSC Checkers for Bose-Lin and Bose Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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In this paper we give a systematic method to design self-exercising (SE) self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-order comparators in the implementation of (k-1)-EC/AUED, (k-1)-EC/d-ED/AUED, (k-1)-EC/d-UED and (k-1)-EC/d-ED/f-UED codes as well as in the design of a fault tolerant cache memory and broadcast networks.