Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A self-checking ALU design with efficient codes
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Self-exercising self testing k-order comparators
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of error detecting codes for the detection of crosstalk originated errors
Proceedings of the conference on Design, automation and test in Europe
Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Energy-reliability trade-off for NoCs
Networks on chip
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
IEEE Transactions on Computers
Checking of combinational circuits basing on modification sum codes
Automation and Remote Control
A modified summation code for organizing control of combinatorial circuits
Automation and Remote Control
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This paper proposes a new class of codes termed "weight-based codes" where each output bit is assigned a weight and the check bits represent the sum of the weights of the output bits which have value '1'. A Berger code is a special member of this proposed class of codes where each output bit is assigned a weight of one. This paper describes the application of these codes for the efficient on-line error detection of arbitrary multilevel circuits. The overall probability of detecting any number of erroneous bits at the output caused by a single internal fault is shown to be higher for weight-based codes than standard error detecting codes. Further, a very efficient design exists for the checker. The checker is area and speed efficient, has low power consumption, and can be tested by a small set of incoming code words. There is always a tradeoff between the fault detection capability and area overhead requirement of an error detecting code. Weight-based codes present a controlled way of increasing the number of check bits to achieve a desired fault detection capability.