A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Logic Complement, a New Method of Checking the Combinational Circuits
Automation and Remote Control
Parity-Scan Design to Reduce the Cost of Test Application
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
New Self-Checking Circuits by Use of Berger-Codes
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Checking Combinational Circuits by the Method of Logic Complement
Automation and Remote Control
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
IEEE Transactions on Computers
A modified summation code for organizing control of combinatorial circuits
Automation and Remote Control
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Organization of functional checking of combinational circuits based on application of modified sum codes is studied. These codes refer to classes of codes with weighted digits and weighted carriers. Properties of codes and techniques for realization of check-out equipment are defined.