The theory of signature testing for VLSI
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Design for Testability A Survey
IEEE Transactions on Computers
Generation of Optimal Transition Count Tests
IEEE Transactions on Computers
A Note on Testing Logic Circuits by Transition Counting
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing
IEEE Transactions on Computers
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Group Theoretic Signature Analysis
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks
IEEE Transactions on Computers
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Aliasing Computation Using Fault Simulation with Fault Dropping
IEEE Transactions on Computers
Programmable BIST Space Compactors
IEEE Transactions on Computers
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Fault Detection in Multiprocessor Systems and Array Processors
IEEE Transactions on Computers
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A new framework for designing & analyzing BIST techniques: computation of exact aliasing probability
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A new test data reduction technique called accumulator compression testng (ACT) is proposed. ACT is an extension of syndrome testing. It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of restricted partitions of a number. Asymptotic results are obtained for independent and dependent error modes. Comparison is made between signature analysis (SA) and ACT. Theoretical results indicate that with ACT a better control over fault coverage can be obtained than with SA. Experimental results are supportive of this indication. Built-in self test for processor environments may be feasible with ACT. However, for general VLSI circuits the complexity of ACT may be a problem as an adder is necessary.