Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Analysis and simulation of parallel signature analyzers
Computers and Mathematics with Applications - Diagnosis and reliable design of VLSI systems
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
| Hi-index | 14.98 |
It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness