Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Low Power BIST for Wallace Tree-Based Fast Multipliers
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On the quality of accumulator-based compaction of test responses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
On Accumulator-Based Bit-Serial Test Response Compaction Schemes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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In this paper we show that an accumulator can bemodified to behave as a Non-Linear Feedback ShiftRegister suitable for test response compaction. Thehardware required for this modification is less than thatrequired to modify a register to a Multiple Input LinearFeedback Shift Register, MISR. We show with experimentson ISCAS'85, ISCAS'89 benchmark circuits and varioustypes of multipliers that the post-compaction faultcoverage obtained by the proposed scheme is higher thanthat of the already known accumulator based compactionschemes and in most cases identical to that achieved usinga MISR.