A novel reseeding technique for accumulator-based test pattern generation

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques

Accumulator-Based Compaction of Test Responses

IEEE Transactions on Computers

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns

IEEE Transactions on Computers

BIST Pattern Generators Using Addition and Subtraction Operations

Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis

A Tutorial on Built-in Self-Test. I. Principles

IEEE Design & Test

Arithmetic Pattern Generators for Built-In Self-Test

ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors

Test response compaction using arithmetic functions

VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium

Methods to reduce test application time for accumulator-based self-test

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Synthesis for Arithmetic Built-In Self-Test

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium

Non-Intrusive BIST for Systems-on-a-Chip

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Arithmetic built-in self test for high-level synthesis

VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium