A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
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Arithmetic built-in self-test (BIST) is a favorable test method for data paths that include adders, subtracters, and other arithmetic units. With these functional units, accumulator structures are configured to generate test patterns and compact test responses.This paper presents a method to synthesize data paths that are well suited for arithmetic BIST. The key part of this approach is an assignment procedure that takes into account structural properties, which are advantageous for arithmetic BIST. The resulting circuits have the same speed and require about the same area as circuits that have been synthesized without testability considerations.