Arithmetic built-in self test for high-level synthesis

Authors:
N. Mukherjee;H. Kassab;J. Rajski;J. Tyszer
Affiliations:
-;-;-;-
Venue:
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Year:
1995

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Abstract

Abstract: In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits.