Computer arithmetic algorithms
Computer arithmetic algorithms
Digital signal processing in VLSI
Digital signal processing in VLSI
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Arithmetic built-in self test for high-level synthesis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Fault Detection in Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Low-Cost On-Line Test for Digital Filters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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This paper presents a new pseudo-exhaustive,test methodology for digital finite impulse response(FIR) filters. The proposed scheme can be employedin a built-in self-test (BIST) environment to detectany combinational faults occum'ng in linear phasecomb filters, trees of sign-extended adders and phase-shiftmultipliers. It wes additive generators as a soumeof pseudo-exhaustive patterns to test systematically allFIR filter building blocks.