IEEE Transactions on Computers
Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
IEEE Transactions on Computers
Design of Diagnosable Iterative Arrays
IEEE Transactions on Computers
Multiple Fault Detection in Arrays of Combinational Cells
IEEE Transactions on Computers
Fault location in cellular arrays
AFIPS '69 (Fall) Proceedings of the November 18-20, 1969, fall joint computer conference
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Self-Diagnosing Cellular Implementations of Finite-State Machines
IEEE Transactions on Computers
Hi-index | 14.99 |
Sufficient conditions are derived that make multidimensional bilateral arrays of combinational cells easily testable for single faults. These conditions are easily implemented during the initial design of the arrays. No restrictions are made on the interconnection patterns or directions of signal flow in the arrays. The conditions are equally applicable to synchronous and asynchronous arrays. No assumptions of stability are made. Any functional fault in a single cell will be detected as long as the failed cell is still combinational. The test sequence is preset and grows linearly with the size of the array.