Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Design of Diagnosable Iterative Arrays
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
Multiple Fault Detection in Arrays of Combinational Cells
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Fault Detection in Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Fault Detection and Design Complexity in C-Testable VLSI Arrays
IEEE Transactions on Computers
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers
On the Testability of One-Dimensional ILAs for Multiple Sequential Faults
IEEE Transactions on Computers
A multi level testability assistant for VLSI design
EURO-DAC '92 Proceedings of the conference on European design automation
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Design-for-testability techniques for CORDIC design
Microelectronics Journal
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Two sets of conditions are derived that make one- dimensional bilateral arrays of combinational cells testable for single faulty cells. The test sequences are preset and, in the worst case, grow quadratically with the size of the array. Conditions for testability in linear time are also derived. The basic cell can operate at the bit or at the word level. An implementation of FIR filters using (systolic) one-dimensional bilateral arrays of cells, which can be considered combinational at the word level, is presented as an example. A straightforward generalization for the two- dimensional case is made; a systolic array used for matrix multiplication is presented as an example for this case.