Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Design of Diagnosable Iterative Arrays
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Design of Testable Structures Defined by Simple Loops
IEEE Transactions on Computers
Fault Detection in Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
CADOC: a system for computed aided functional test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.