Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
| Hi-index | 14.99 |
It is shown that one-dimensional, unilateral iterative logic arrays (ILAs) of combinational cells are C-testable for multiple sequential faults, provided the fault-free cell functions satisfy appropriate conditions. The test sequence is of length O((m/sup 2/n/sup 2/+mn/sup 3/)*K), where n (resp. m) is the number of signal values that can be applied to the horizontal (resp. vertical) cell input and Kor=n-1. Linear testability is also considered. The ripple-carry adder circuit (n=2, m=4) is shown to be C-testable with 699 test vectors.