Logic testing and design for testability
Logic testing and design for testability
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
VLSI array processors
On Functional Testing of Array Processors
IEEE Transactions on Computers
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
IEEE Transactions on Computers
Testing and diagnosis of FFT arrays
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
Multiple Fault Detection in Arrays of Combinational Cells
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Hi-index | 0.00 |
In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, Aladin. This tool operates as a Testability Analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design.