Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Testing and error detection in iterative logic arrays
Testing and error detection in iterative logic arrays
A multi level testability assistant for VLSI design
EURO-DAC '92 Proceedings of the conference on European design automation
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors present a novel approach to the test generation problem for a more general class of two-dimensional iterative logic arrays (ILAs) than considered by previous researchers. For certain ILAs it is possible to find a test set whose size remains fixed irrespective of the size of the ILA, while for others it varies with array size. Given an arbitrary ILA cell truth table and a cell interconnection structure, the goal is to determine if a fixed-size test can be found. If not, then a test set whose size grows as slowly as possible with the size of the array should be found. The authors propose a new model, called the n-cube of cell states model, for representing the cell truth table and interconnection structure. The test generation problem is shown to be related to certain properties of cycles in a set of graphs obtained from this model. By careful analysis of these cycles, efficient testing schedules can be obtained. The proposed technique can be applied to unilateral as well as regular bilateral ILAs in which the bilateral direction of signal flow are restricted to lie along the horizontal axis.