A Note on Testing Logic Circuits by Transition Counting
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
IEEE Transactions on Computers
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The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.