Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
A unified view of test compression methods
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms
Integration, the VLSI Journal
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Genetic algorithms + data structures = evolution programs (2nd, extended ed.)
Genetic algorithms + data structures = evolution programs (2nd, extended ed.)
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Shift Register Sequences
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Genetic Algorithms for the Traveling Salesman Problem
Proceedings of the 1st International Conference on Genetic Algorithms
Built-in Self-testing of Logic Circuits Using Imperfect Duplication
FCT '87 Proceedings of the International Conference on Fundamentals of Computation Theory
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Implementing Semantic Network Structures Using the Classifier System
Proceedings of the 1st International Conference on Genetic Algorithms
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Machine learning procedures for generating image domain feature detectors
Machine learning procedures for generating image domain feature detectors
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits
WIA '99 Revised Papers from the 4th International Workshop on Automata Implementation
4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Journal of Computer Science and Technology
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
We address test data compaction for built-in self-test (BIST). We propose a novel taxonomy useful for classifying and comparing BIST compactors. The taxonomy uses the following attributes: space, time, memory, linearity, and circuit (functional) specificity. The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set of test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area. Results reveal that we can find PSCs with better fault coverage and cost characteristics than the parity function using modest computing resources, e.g., PSCs with equal or greater fault coverage than the parity function for as little as 20% of the cost (in terms of gate count) with an investment of only a few hours of workstation computing time.