Programmable BIST Space Compactors
IEEE Transactions on Computers
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Abstract: Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking a MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method.