Journal of Electronic Testing: Theory and Applications
Programmable BIST Space Compactors
IEEE Transactions on Computers
Zero-aliasing space compaction of test responses using multiple parity signatures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper output space compaction for sequential circuits is considered for the first time. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions can be determined without fault simulation. The outputs are partitioned in such a way that internal stuck-at faults influence at most one of the outputs of a group with high probability. The proposed method is primarily developed for concurrent checking. On average with less than 4 compacted groups of outputs an error detection probability of 98% can be achieved. As the experimental results show, the method is also effectively applicable in pseudo-random test mode. On average for three groups of compacted outputs there is no reduction of the fault coverage for a pseudo-random off-line test. Since the proposed algorithm is of linear complexity with respect to the number of circuit lines and of quadratic complexity with respect to the number of primary circuit outputs large automata can be efficiently processed.