16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST

Authors:
M. Gössel M. Seurin;E. Sogomonyan
Affiliations:
-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 9
Cited 4

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Abstract

In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits.