Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
A Structural Method for Output Compaction of Sequential Automata Implemented as Circuits
WIA '99 Revised Papers from the 4th International Workshop on Automata Implementation
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Aliasing-Free Space and Time Compactions with Limited Overhead
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
Cost-Driven Selection of Parity Trees
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reunion: Complexity-Effective Multicore Redundancy
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Built-in self-testing requires test response streams from many observation points to be merged (space compaction) and compressed (time compaction) into a short signature. The compaction circuits should be transparent to error propagation in order to minimize aliasing, which occurs when a faulty response maps to the fault-free signature. We investigate the use of multiplexed parity trees (MPTs) for zero-aliasing space compaction. MPTs combine the error propagation properties of multiplexers and parity trees, and ensure zero aliasing via multistep compaction. We present two design techniques based on MPTs-output selection and fanout insertion-that eliminate aliasing for both deterministic and pseudorandom test sets. Our experiments with the ISCAS benchmark circuits show that zero aliasing can be achieved with small test sets and moderate hardware overhead. We also demonstrate that a very high percentage of single stuck-line faults in the compaction circuit are detected by the test patterns applied to the circuit under test