Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
Design of Self-Checking Sequential Machines
IEEE Transactions on Computers
Concurrent Error Detection Using Monitoring Machines
IEEE Design & Test
Self-Checking Design in Eastern Europe
IEEE Design & Test
Space and time compaction schemes for embedded cores
Proceedings of the IEEE International Test Conference 2001
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Microprocessors & Microsystems
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We discuss a non-intrusive methodology for concurrent error detection in FSMs. The proposed method is based on compaction and monitoring of the state/output bits of an FSM via parity trees. While errors may affect more than one state/output bit, not all combinations of state/output bits constitute potential erroneous cases for a given fault model. Therefore, it is possible to compact them without loss of error information. Thus, concurrent error detection is performed through hardware that predicts the values of the compacted state/output bits and compares them to the actual values of the FSM. In order to minimize the incurred hardware overhead, a randomized algorithm is proposed for selecting the minimum number of required parity functions.