Design of Self-Checking Sequential Machines

Authors:
S. Dhawan;R. C. De Vries
Affiliations:
IBM, Austin, TX;Univ. of New Mexico, Albuquerque
Venue:
IEEE Transactions on Computers
Year:
1988

Citing 0
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Abstract

The authors present the design of self-checking sequential machines using standard memory elements, i.e. D, T, or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D, T, and JK flip-flops and for transmitting errors from their inputs to their outputs are presented; these are shown to exist in normal operation when the design procedure is used. SR flip-flops are found not to have the properties necessary for designing self-checking sequential machines.