Programmable BIST Space Compactors
IEEE Transactions on Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-aliasing space compaction using linear compactors with bounded overhead
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Testing embedded cores in a System-on-a-chip necessitatesthe use of a Test Access Mechanism, which provides fortransportation of the test data between the chip and the coreI/Os. We outline an aliasing-free space and time compactionscheme, for both combinational and sequential cores, whichminimizes the required test bandwidth and reduces the bandwidthconsumption of the Test Access Mechanism at the coreoutput side. The experimental results show that the test bandwidthgain is achieved with no appreciable increase in testapplication time.