Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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A structure-independent method for space compaction based on a new generic scheme is presented in this paper. The compactor compresses test responses of a circuit-under-test (CUT) to a single periodic data stream with guaranteed zero-aliasing, and can be designed only from the knowledge of the test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT, also detects all multiple stuck-at faults in the response logic, and almost all the faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design does not need any structural information of the CUT, it is useful for testing embedded cores.