Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Using On-chip Test Pattern Compression For Full Scan SoC Designs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. It is shown that given a precomputed test set T, the test responses at the functional outputs of the given circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero-aliasing. The method is independent of the fault model and the structure of the CUT, and uses only the knowledge of the test set T and the corresponding fault-free responses|it is particularly suitable for intellectual property (IP) cores. A new concept of distinguishing outputs and characteristic response function is utilized for synthesizing the compactor. Relevant experimental results on hardware overhead for several ISCAS circuits are presented.