Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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In todays mixed signal System-on-Chip designs advancedDesign-for-Test techniques become more and more importantto meet test coverage and quality requirements. However,standard strategies often cannot be used because ofdesign specific requirements like the limitation of availableinput and output pins.This paper describes the Design-for-Test strategy of thelatest version of Motorola's chip family for a mixed signalapplication. Deterministic test pattern, which are generatedusing an ATPG tool, have been used to stimulate thedesign and achieve efficient and high test coverage. Thememories are tested by using a memory BIST implementation.The limitation of available digital input and outputpins is solved in two ways. Analog input pins have beenmodified to serve as digital pins in test mode. On-chip testpattern compression using a multiple input shift register(MISR) is used to reduce the number of required outputpins. Failure diagnostic capabilities have been implementedto allow debug of failing devices. The paper describes the test strategy for the System-on-Chip device and outlines the design flow which was used to implement it.