A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Hierarchical testing using precomputed tests for modules
Hierarchical testing using precomputed tests for modules
Programmable BIST Space Compactors
IEEE Transactions on Computers
Zero-Aliasing for Modeled Faults
IEEE Transactions on Computers
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An improved output compaction technique for built-in self-test in VLSI circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A structural study and algorithms in vertex coloring
A structural study and algorithms in vertex coloring
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-aliasing space compaction using linear compactors with bounded overhead
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shrinking wide compressors [BIST]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Journal of Computer Science and Technology
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
IEICE - Transactions on Information and Systems
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 14.98 |
Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q 1.