Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
Space and time compaction schemes for embedded cores
Proceedings of the IEEE International Test Conference 2001
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
Test response compaction using multiplexed parity trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero-aliasing space compaction using linear compactors with bounded overhead
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Test bandwidth allocation issues greatly limit parallel testing of SoC cores. Here, the authors propose a response compaction methodology for reducing the required output core bandwidth, enabling increased parallelism among core tests and hence reducing overall SoC test time.