Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
A built-in self test scheme for VLSI
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Salvaging test windows in BIST diagnostics
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Compactor Independent Direct Diagnosis
ATS '04 Proceedings of the 13th Asian Test Symposium
FAULT DIAGNOSIS IN DESIGNSWITH CONVOLUTIONAL COMPACTORS
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finite memory test response compactors for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Machine learning-based volume diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.98 |
Column Selection Row Parity (CPRS) diagnosis is an X-tolerant and low aliasing technique that is suitable for the BIST environment. A row selection LFSR randomly selects outputs of multiple scan chains so that unknowns can be tolerated. Column and row parities of selected outputs are observed to solve linear equations for the error positions. Experimental data show that CPRS achieves nearly perfect diagnosis, even in the presence of 1 percent unknowns. CPRS compresses the diagnosis data because only parities of circuit responses, instead of responses themselves, are observed. Two error distribution models (scattered and clustered) are developed and analyzed to show the effectiveness of CPRS. The analytical results are demonstrated to be accurate by more than 10,000 experiments.