Meeting Nanometer DPM Requirements Through DFT
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Value-Added Defect Testing Techniques
IEEE Design & Test
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Dynamic learning based scan chain diagnosis
Proceedings of the conference on Design, automation and test in Europe
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Fault diagnosis aware ATE assisted test response compaction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
Test-data volume optimization for diagnosis
Proceedings of the 49th Annual Design Automation Conference
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In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.