Scalable selector architecture for x-tolerant deterministic BIST

  • Authors:
  • Peter Wohl;John A. Waicukauski;Sanjay Patel

  • Affiliations:
  • Synopsys Inc., Williston, VT;Synopsys Inc., Tualatin, OR;Synopsys Inc., Beaverton, OR

  • Venue:
  • Proceedings of the 41st annual Design Automation Conference
  • Year:
  • 2004

Quantified Score

Hi-index 0.00

Visualization

Abstract

X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full X-tolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG.