Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
IEICE - Transactions on Information and Systems
Post-BIST Fault Diagnosis for Multiple Faults
IEICE - Transactions on Information and Systems
Experimental comparison of different diagnosis algorithms in the BIST environment
ASM '07 The 16th IASTED International Conference on Applied Simulation and Modelling
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.04 |
We present a new scan built-in self-test (BIST) approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test, and it is especially suitable for faults that are detected by a relatively small number of pseudorandom test patterns. Two multiple-input signature registers are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and fault-free intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We propose a signature-analysis method based on overlapping sections and the principle of superposition to effectively prune the candidate set. We present analytical results to determine an appropriate interval length and the degree of overlap, as well as upper and lower bounds on the size of S. We also determine a lower bound on the number of true failing vectors through a simple graph model. Finally, we present experimental results for the ISCAS'89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.