Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
A simple technique for locating gate-level faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Diagnosis Of Byzantine Open-Segment Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Persistent Diagnostic Technique for Unstable Defects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests
ATS '04 Proceedings of the 13th Asian Test Symposium
On per-test fault diagnosis using the X-fault model
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect Open Defect Diagnosis with Physical Information
ATS '06 Proceedings of the 15th Asian Test Symposium
Fanout-based fault diagnosis for open faults on pass/fail information
ATS '06 Proceedings of the 15th Asian Test Symposium
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In order to reduce the test cost, built-in self test (BIST) is widely used. One of the serious problems of BIST is that the compacted signature in BIST has very little information for fault diagnosis. Especially, it is difficult to determine which tests detect a fault. Therefore, it is important to develop an efficient fault diagnosis method by using incompletely identified pass/fail information. Where the incompletely identified pass/fail information means that a failing test block consists of at least one failing test and some passing tests, and all of the tests in passing test blocks are the passing test. In this paper, we propose a method to locate open faults by using incompletely identified pass/fail information. Experimental results for ISCAS'85 and ITC'99 benchmark circuits show that the number of candidate faults becomes less than 5 in many cases.