Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
Group Theoretic Signature Analysis
IEEE Transactions on Computers
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
IEEE Transactions on Computers
Programmable BIST Space Compactors
IEEE Transactions on Computers
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Correction to "A Data Compression Technique for Built-In Self-Test"
IEEE Transactions on Computers
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
Diagnosis by Signature Analysis of Test Responses
IEEE Transactions on Computers
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
An improved output compaction technique for built-in self-test in VLSI circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Aliasing-Free Space and Time Compactions with Limited Overhead
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
IEEE Transactions on Computers
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
Journal of Integrated Design & Process Science
Efficient test response compression for multiple-output circuits
ITC'94 Proceedings of the 1994 international conference on Test
Altera max plus II development environment in fault simulation and test implementation of embedded
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Implementation of embedded cores-based digital devices in JBits java simulation environment
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
| Hi-index | 15.01 |
A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed. It is argued that the proposed data-compression technique reduce the hardware complexity in built-in self-test (BIST) logic designs using external tester environments.