Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
IEEE Transactions on Computers
Test response compaction for built-in self testing
Test response compaction for built-in self testing
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
IEEE Design & Test
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This paper proposes test design architecture suitable for built-in self-testing (BIST) of embedded cores-based digital circuits by using a reconfigurable device. In the paper, a sample circuit under test (CUT) and its corresponding space compressor were realized in Java language, downloaded, and then tested at runtime in a simulation environment written in JBits.