Altera max plus II development environment in fault simulation and test implementation of embedded

Authors:
Sunil R. Das;Chuan Jin;Liwu Jin;Mansour H. Assaf;Emil M. Petriu;Mehmet Sahinoglu
Affiliations:
School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada;School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada;School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada;School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada;School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada;Department of Computer and Information Science, Troy State University Montgomery, Montgomery, AL
Venue:
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Year:
2004

Citing 9
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Abstract

A Verilog HDL-based fault simulator for testing embedded cores-based synchronous sequential circuits is proposed in the paper to detect single stuck-line faults The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a CUT (circuit under test) and the output streams from the CUT are fed into a response data analyzer. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The subject paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 full-scan sequential benchmark circuits are also provided.