A unified view of test compression methods
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
A Statistical Theory of Digital Circuit Testability
IEEE Transactions on Computers
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Analysis and Design of Linear Finite State Machines for Signature Analysis Testing
IEEE Transactions on Computers
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Parallel Signature Analysis Design with Bounds on Aliasing
IEEE Transactions on Computers
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
IEEE Transactions on Computers
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
Counter-Based Compaction: Delay and Stuck-Open Faults
IEEE Transactions on Computers
Can Nonlinear Compactors Be Better than Linear Ones?
IEEE Transactions on Computers
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the quality of accumulator-based compaction of test responses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Comments on “Test efficiency analysis of random self-test of sequential circuits”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper discusses a systematic methodology for calculating the exact aliasing probability associated with schemes that use an arbitrary finite-state machine to compact the response of a combinational circuit to a sequence of independently selected, random test input vectors. The proposed approach identifies the strong influence of fault activation probabilities on the probability of aliasing and uses an asymmetric error model to simultaneously track the states of two (fictitious) compactors, one driven by the response of the fault-free combinational circuit and one driven by the response of the faulty combinational circuit. By deriving the overall Markov chain that describes the combined behavior of these two compactors, we are able to calculate the exact aliasing probability for any test sequence length. In particular, for long enough sequences, the probability of aliasing is shown to only depend on the stationary distribution of the Markov chain. The insights provided by our analysis are used to evaluate the testing performance of simple examples of nonlinear compactors and to demonstrate regimes where they exhibit lower aliasing probability than linear compactors with the same number of states. Finally, by establishing connections with previous work that evaluated aliasing probability in linear compactors, our analysis clarifies the role played by the entropy of the stationary distribution of the compactor states.