Test generation for digital systems
Fault-tolerant computing: theory and techniques; vol. 1
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Comments on 'Signature Analysis for Multiple Output Circuits' by R. David
IEEE Transactions on Computers
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
Counter-based compaction: an analysis for BIST
Journal of Electronic Testing: Theory and Applications
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
IEEE Transactions on Computers
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In this paper, we study the properties of all major counter-based compaction schemes when the circuit under test is affected by delay or stuck-open faults. We present an error model that accurately describes the behavior of such circuits. The error model inherits from the asymmetric error model [1] and the model used in [2]. Using this model, we compute exact aliasing probability for any test session length; we also determine the asymptotic aliasing probability. Examples that compare aliasing in counter-based compaction with aliasing in LFSRs indicate that the latter is more 驴predictable.驴